Abstract: This project presents a scheme for detecting and diagnosing faults that are commonly occurred random access memory and Read only memory. The build in self test technique is used to identify permanent failures in embedded memories. The target of the project is fault detection and diagnosis in ROM and RAM such as single cell faults, row and column wise faults using Build in self test. In all the proposed test methods, Design for Test and Built-In Self-Test techniques have been proven to be very effective by the meaning of increasing the observability and controllability of the Circuit under Test thus fault is detected so as to increase the reliability of the memories. The proposed approach offers a simple test flow and does not require intensive interactions between a Build in Self Test controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. The signature is created for comparing the faulty cell and it is compared with the array of rows and columns. If there present the mismatch of signature already available with the testing cell then the fault is detected. Thus this project is designed to meet requirements of high-speed automatic test thus enabling detection of timing defects. It produces efficient way of identifying faults in memories.

Keywords: SRAM Read Only Memory (ROM), Random Access Memory (RAM).